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Resource usage for nRF52

CPU usage

Mira normally use at most 25% of the CPU measured over a 40ms window. Some infrequent processing uses the CPU, at thread/appplication level, for longer periods.

Note that delaying the SWI IRQ handler or IRQ handlers above priority 2 will decrease Mira's network performance.

Mira will drop further received packets until it has processed it at thread/application level. That will also lead to decreased network performance.

SoftDevice

For platforms using SoftDevice, see Nordic Semiconductor's S132/S140 SoftDevice Specification for its hardware requirements.

Mira uses the Radio Timeslot API, that makes it unavailable to other applications.

MiraOS consumes the SoftDevice events. To use them in an application, see here.

MiraMesh needs to have the SoftDevice events forwarded to it, see here.

Peripherals used by MiraOS

Some resources are available for direct access if special low level access is required. Others are available via specific APIs or used internally by Mira OS.

To use the peripherals of nRF52 directly, refer to the corresponding nRF52 product specification for information.

  • Cells marked ✅ are available for application.
  • Cells marked ⚠️ proviedes restricted access.
  • Cells marked ❌ are not available for application.
Peripheral nrf52832 nrf52832ble nrf52840 nrf52840ble
AAR ❌ ❌ ❌ ❌
ACL/BPROT ✅10 ✅10 ✅10 ✅10
CCM ❌ ❌ ❌ ❌
CLOCK ❌ ❌ ❌ ❌
COMP ✅1 ✅1 ✅1 ✅1
CRYPTOCELL ✅ ✅
ECB ❌ ❌ ❌ ❌
FPU ✅2 ✅2 ✅2 ✅2
GPIOTE ❌ ❌ ❌ ❌
I2S ✅ ✅ ✅ ✅
LPCOMP ✅1 ✅1 ✅1 ✅1
MWU ❌ ❌ ❌ ❌
NFCT ❌ ❌ ❌ ❌
NVMC ❌ ❌ ❌ ❌
P0 (GPIO) ⚠️3 ⚠️3 ⚠️3 ⚠️3
P1 (GPIO) ⚠️3 ⚠️3
PDM ✅ ✅ ✅ ✅
POWER ❌ ❌ ❌ ❌
PPI ⚠️4 ⚠️4 ⚠️4 ⚠️4
PWM0 ✅ ✅ ✅ ✅
PWM1 ✅ ✅ ✅ ✅
PWM2 ✅ ✅ ✅ ✅
PWM3 ✅ ✅
QDEC ✅ ✅ ✅ ✅
QSPI5 ✅ ✅
RADIO ❌ ❌ ❌ ❌
RNG ❌ ❌ ❌ ❌
RTC0 ✅ ❌ ✅ ❌
RTC1 ✅ ✅ ✅ ✅
RTC2 ❌ ❌ ❌ ❌
SAADC ⚠️6 ⚠️6 ⚠️6 ⚠️6
SPIM0/SPIS0/SPI0 ⚠️7 ⚠️7 ⚠️7 ⚠️7
SPIM1/SPIS1/SPI1 ⚠️7 ⚠️7 ⚠️7 ⚠️7
SPIM2/SPIS2/SPI2 ⚠️7 ⚠️7 ⚠️7 ⚠️7
SPIM3 ⚠️7 ⚠️7
SWI0/EGU0 ❌ ❌ ❌ ❌
SWI1/EGU1 ❌ ❌ ❌ ❌
SWI2/EGU2 ❌ ❌ ❌ ❌
SWI3/EGU3 ❌ ❌ ❌ ❌
SWI4/EGU4 ✅ ✅ ✅ ✅
SWI5/EGU5 ❌ ❌ ❌ ❌
TEMP ❌ ❌ ❌ ❌
TIMER0 ❌ ❌ ❌ ❌
TIMER1 ❌ ❌ ❌ ❌
TIMER2 ❌ ❌ ❌ ❌
TIMER3 ✅ ✅ ✅ ✅
TIMER4 ✅ ✅ ❌8 ❌8
TWIM0/TWIS0/TWI0 ⚠️7 ⚠️7 ⚠️7 ⚠️7
TWIM1/TWIS1/TWI1 ⚠️7 ⚠️7 ⚠️7 ⚠️7
UARTE0/UART0 ⚠️9 ⚠️9 ⚠️9 ⚠️9
UARTE1/UART1 ⚠️9 ⚠️9
USBD ✅ ✅
WDT ❌ ❌ ❌ ❌

PPI availability with MiraOS

PPI nrf52832 nrf52832ble nrf52840 nrf52840ble
channel 0-12 ❌ ❌ ❌ ❌
channel 13-16 ✅ ✅ ✅ ✅
channel 17-31 ❌ ❌ ❌ ❌
group 0-5 ❌ ❌ ❌ ❌

PPI availability with MiraMesh

MiraMesh use two configurable PPIs and one configurable PPI group.

Interrupts used by MiraMesh

MiraMesh is only available with SoftDevice.

Besides SoftDevice's hardware requirements, MiraMesh also use one configurable RTC, one configurable SWI/EGU IRQ and the SWI1/EGU1 IRQ.

The integration code must call miramesh_rtc_irq_handler and miramesh_swi_irq_handler for their IRQs. It should also call miramesh_swi1_irq_handler for SWI1/EGU1 IRQ.

The confirgured SWI IRQ need to have a priority between 1 and the RTC's IRQ priority.

Interrupts used by MiraOS

MiraOS is delivered with an isr_vector.c file containing the ISR vector. MiraOS has default IRQ handlers for unused IRQs. They are weak and can be overridden by defining a function with the same name.

If MiraOS' HAL isn't used for a peripheral, its IRQ is free and an external ISR handler can be used.

With MiraOS 2.4.0 and 2.4.1 the IRQ handler's name isn't weak and an external IRQ handler need to have a unique name. That name must to be put in the isr_vector.

With later versions of MiraOS, MiraOS' IRQ handlers have a mira_-prefix, leaving the default names free for use.

IRQ Priorities

IRQ/Event Prio
GPIOTE 7
NFCT 7
POWER/CLOCK 1
RADIO 0
Reset -
RNG 3
RTC2 6
SAADC 5
SPIM0/SPIS0/TWIM0/TWIS0/SPI0/TWI0 5
SPIM1/SPIS1/TWIM1/TWIS1/SPI1/TWI1 7
SPIM2/SPIS2/SPI2 7
SoftDevice Event 7
SoftDevice Radio Event 0
SWI0/EGU0 5
TIMER0 0
TIMER4 7
UARTE0/UART0 3
WDT 7

Notes

  1. LPCOMP/COMP can not use the same analog input as the ADC, when using Mira API for the ADC
  2. Errata 87 fix for nrf52840 implemented
  3. Only PIN_CNF[n], OUTSET/OUTCLR, DIRSET/DIRCLR are availavble for pins not managed by Mira API
  4. Some PPI channels are available, see separate table
  5. QSPI pins might not be available for all modules
  6. Available when ADC is not used via Mira API
  7. Available only when not using either SPI or I2C via Mira API
  8. Available when NFC is not used via Mira API
  9. Available when UART is not used via Mira API
  10. Make sure it doesn't hinder access from MiraOS to the SWAP area for the FOTA driver and CONFIG0/1 for mira_userconfig_*() if those APIs are used.